1. Field of the Invention
The present invention relates in general to wafer-level integrated circuit (IC) testers, and in particular to a method for verifying signal paths through a structure interconnecting an IC tester to an IC wafer to be tested.
2. Description of Related Art
Many integrated circuit (IC) testers test ICs while the ICs are still in the form of die on a semiconductor wafer. A typical wafer tester includes a chassis called a xe2x80x9ctest headxe2x80x9d containing printed circuit boards implementing the circuits that test a wafer. The test circuits are usually organized into a set of similar xe2x80x9cchannelsxe2x80x9d, with each channel including all the circuitry needed to generate a test signal input to one test point on the wafer and to monitor any wafer output signal produced at that test point. Each channel usually has a single bit-directional input/output (I/O) port through which it communicates with the wafer test point, though some employ two unidirectional ports.
An interconnect structure residing between the test head and the wafer provides signal paths between the channels"" I/O ports and test points on the wafer. Interconnect structures make contact with the test head I/O ports and the wafer test points in various ways. For example with the test head residing above the interconnect structure, a channel""s I/O port may access contact pads on an upper surface of a interconnect structure via a set of pogo pin connectors extending downward from the test head. The interconnect structure in turn may access the test points of the IC die via a set of small probes. The probes may be attached to an under surface of an interconnect structure and may contact pads on the upper surface of the wafer when the wafer is moved into position under the interconnect structure. Alternatively, the probes may be implemented as spring contacts formed on the surface of the wafer itself, with tips of the spring contacts accessing contact pads on the under surface of interconnect structure.
Since the test head is relatively large, the tester channels"" I/O ports are distributed over a much wider horizontal area than the test points on the relatively small IC die they must access. Thus regardless of how the interconnect structure is implemented, it must provide a large number of signal paths extending in both horizontal and vertical directions in order to interconnect the channel I/O ports to the test points on the wafer. Thus the interconnect structure is often a relatively complicated structure including more than one interconnected signal routing layer. The signal paths through the interconnect structure may also include components such as small resistors or capacitors.
Before testing a wafer we would like to confirm that the interconnect structure can provide the necessary signal paths between the test head and the wafer. A connection failure may arise, for example, due to a misalignment of pogo pins or probes with their intended contact points, a broken, missing or contaminated pogo pin, probe or contact pad, a misalignment between contact structures within internal layers within the interconnect structure, an open circuit or short circuit fault between conductors within the interconnect structure or within the test head, or defective or missing discrete components in the signal paths through the interconnect structure. In many applications we also would like to verify that the resistance of a signal path between each test head I/O port and a corresponding test point on wafer is within acceptable limits. Contactor assemblies are usually designed to provide signal paths having particular resistances, and any variation from the intended resistance, due for example to corrosion or contamination on contact pads or the tips of probes or pogo pins, can distort test results.
Shorts, continuity and resistances of signal paths within a interconnect structure are usually tested during the manufacturing process using conventional resistance and continuity testing equipment accessing opposite ends of the signal paths via small probes. However signal paths within a probe assembly can later fail when in use in an integrated circuit tester, and it is difficult and inconvenient to periodically remove a probe assembly from a tester and manually test the continuity and resistance of its signal paths. Open and short circuit signal path failures can often be detected, or at least suspected, because they usually lead to characteristic patterns of IC test failures. However when a signal path has a resistance that is marginally out of an acceptable range, wafer test failures may not exhibit a clear pattern, and die can be improperly rejected as failing a test when the source of the failure was in fact the interconnect structure.
What is needed is a convenient method for quickly testing for shorts, continuity and resistances of signal paths through a interconnect structure without having to remove it from its working environment.
A interconnect structure typically provides multiple signal paths between input/output (I/O) ports of an integrated circuit (IC) tester and test points of an IC wafer to be tested. In accordance with one aspect of the invention, the ability of the interconnect structure to connect the IC tester""s I/O ports to the wafer""s test points is verified by first employing the interconnect structure to interconnect those I/O ports to a similar arrangement of test points on a reference wafer.
The reference wafer, similar in size and shape to the wafer to be tested, includes conductors linking groups of the test points. When the tester generates a test signal at one of its I/O ports, that signal travels through the interconnect system to a test point on the reference wafer. A conductor within the wafer then conveys the test signal to another of the test points. The test signal then travels from that reference point back through the interconnect structure to another I/O port of the IC tester. The continuity of signal path from any tester I/O port to a test point on the reference wafer can therefore be tested by programming the tester to transmit a test signal to the reference wafer via that I/O port and to look for the signal as it returns via another of the I/O ports.
The resistance of a signal paths through the interconnect structure is measured by transmitting signals of known current between I/O ports linked through those signal paths and the reference wafer and to measure the voltage drop between the two I/O ports. Alternatively the tester may place a known voltage across two linked I/O ports and measure the current passing between them. In either case the resistance of the system signal path between the two ports is then computed from the test signal voltage and current. When this procedure is repeated to measure resistance between various combinations of I/O ports, the path resistance between each tester I/O port and the wafer test point to which it is connected can be computed from the results.
Shorts between a selected signal path and any other signal path through the interconnect structure can be tested by removing the reference wafer, programming one tester channel to apply a test signal to the selected signal path and programming other tester channels to look for the appearance of that signal on the other signal paths.
It is accordingly an object of the invention to provide means for verifying that an interconnect system is capable of providing continuous signal paths between ports of an IC tester and test points on a wafer to be tested.
It is another object of the invention to provide means for measuring resistance of signal paths through a interconnect structure linking ports of an IC tester and test points on the wafer to be tested.
The concluding portion of this specification particularly points out and distinctly claims the subject matter of the present invention. However those skilled in the art will best understand both the organization and method of operation of the invention, together with further advantages and objects thereof, by reading the remaining portions of the specification in view of the accompanying drawing(s) wherein like reference characters refer to like elements.